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info:vhdl [2022/11/07 14:44] francois |
info:vhdl [2022/11/23 09:07] (current) francois [VHDL Xilinx/Modelsim] |
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| Below you'll find some links either related to the VHDL courses, practical exercises and some external links: | Below you'll find some links either related to the VHDL courses, practical exercises and some external links: | ||
| - | * <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_course.pdf|VHDL]] main course, | + | * <wrap em>VHDL main course</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL_course.pdf|PDF]], |
| - | * <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL4synthesis_practical_exercises.pdf|VHDL4synthesis]] practical exercises,\\ | + | * <wrap em>VHDL synthesis practical exercices</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL4synthesis_practical_exercises.pdf|PDF]],\\ |
| - | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/R3K_Base|Master2 VHDL base files]] to download, | + | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M2|Master2 VHDL base files]] to download, |
| * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | ||
| ===== Links ===== | ===== Links ===== | ||
| - | * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]] | ||
| * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]] | * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]] | ||
| - | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|reference manual]] | + | * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]] |
| - | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7_schematic-D1.pdf|schematic]] | + | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 reference manual</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|PDF]] |
| + | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 schematic</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7_schematic-D1.pdf|PDF]] | ||
| - | * <wrap em>[boak]</wrap>The Zynq eBook [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/The_Zynq_Book_ebook_3.pdf|PDF]] | + | * <wrap em>[book]</wrap> The Zynq eBook [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/The_Zynq_Book_ebook_3.pdf|PDF]] |
| * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | ||
| * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | ||
info/vhdl.1667832283.txt.gz · Last modified: 2022/11/07 14:44 by francois
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