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info:vhdl [2021/12/23 23:38] francois |
info:vhdl [2022/11/23 09:07] (current) francois [VHDL Xilinx/Modelsim] |
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| In a near future, we'll experiment the [[http://cdn.gowinsemi.com.cn/DS861E.pdf|GoWin GW1NSR-LV4C]] which embedds an <wrap em>ARM Cortex-M3 + FPGA</wrap> like what's done in Xilinx Zynq.\\ | In a near future, we'll experiment the [[http://cdn.gowinsemi.com.cn/DS861E.pdf|GoWin GW1NSR-LV4C]] which embedds an <wrap em>ARM Cortex-M3 + FPGA</wrap> like what's done in Xilinx Zynq.\\ | ||
| - | Additionnally, i'd like to thanks GoWin //(thanks Danny)// that provided us sevreal Ministar development kits along with 30 seats floating licence :)\\ | + | Additionally, i'd like to thanks [[https://www.gowinsemi.com/|GoWin semi conductors]] //(thanks Danny)// that provided us sevreal {{ :vhdl:gowin-ministar-dev-kit.png?linkonly|Ministar development kits}} along with 30 seats floating licence :)\\ |
| More to come, stay tuned ;-) | More to come, stay tuned ;-) | ||
| \\ | \\ | ||
| <WRAP leftalign round info 60%>//**__Xilinx Vivado Student edition__**// | <WRAP leftalign round info 60%>//**__Xilinx Vivado Student edition__**// | ||
| - | Xilinx offers to download the Xilinx [[http://www.xilinx.com/products/design_tools/vivado/vivado-webpack.htm|Vivado Webpack]] edition. This will enable you to work on your own with the same toolchain we're using in this formation. | + | Xilinx offers to download the Xilinx [[https://www.xilinx.com/support/university/students.html#software|Vivado Webpack]] edition. This will enable you to work on your own with the same toolchain we're using in this formation. |
| </WRAP> | </WRAP> | ||
| Line 18: | Line 18: | ||
| <WRAP leftalign round info 60%>//**__ModelSim Student edition__**// | <WRAP leftalign round info 60%>//**__ModelSim Student edition__**// | ||
| MentorGraphics' [[http://www.modelsim.com|Modelsim]] is the simulation tool we will use. As a Master2 student, just ask them for a licence you will obtain in a few weeks. | MentorGraphics' [[http://www.modelsim.com|Modelsim]] is the simulation tool we will use. As a Master2 student, just ask them for a licence you will obtain in a few weeks. | ||
| - | </WRAP> | ||
| - | |||
| - | <WRAP leftalign round info 60%>//**__SDSoc toolchain__**// | ||
| - | This toolchain enables you to implement as a hardware coprocessor part(s) of an application. | ||
| </WRAP> | </WRAP> | ||
| Line 28: | Line 24: | ||
| Below you'll find some links either related to the VHDL courses, practical exercises and some external links: | Below you'll find some links either related to the VHDL courses, practical exercises and some external links: | ||
| - | * <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_course.pdf|VHDL]] main course, | + | * <wrap em>VHDL main course</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL_course.pdf|PDF]], |
| - | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_practical_exercises.pdf|VHDL practical exercises]], | + | * <wrap em>VHDL synthesis practical exercices</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL4synthesis_practical_exercises.pdf|PDF]],\\ |
| - | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/R3K_Base|VHDL base files]] to download, | + | |
| + | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M2|Master2 VHDL base files]] to download, | ||
| * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | ||
| - | * [[http://opencores.org|Opencores]] repository, | + | |
| + | ===== Links ===== | ||
| + | |||
| + | * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]] | ||
| + | * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]] | ||
| + | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 reference manual</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|PDF]] | ||
| + | * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 schematic</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7_schematic-D1.pdf|PDF]] | ||
| + | |||
| + | * <wrap em>[book]</wrap> The Zynq eBook [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/The_Zynq_Book_ebook_3.pdf|PDF]] | ||
| + | * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | ||
| + | * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | ||
| + | * Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform, | ||
| + | |||
| + | * INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]], | ||
| + | * [[http://opencores.org|Opencores]] repository. | ||
info/vhdl.1640302702.txt.gz · Last modified: 2021/12/23 23:38 by francois
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