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--- info:vhdl [2018/10/19 09:16]
francois
+++ info:vhdl [2022/11/23 09:07] (current)
francois [VHDL Xilinx/Modelsim]
@@ Line 1: / Line 1: @@
 ====== VHDL Xilinx/Modelsim ======
 \\
-{{ :vhdl:parallella.png?direct&300|Parallella board}}
+{{ :vhdl:xilinx-zybo.png?direct&250|Xilinx Zynq Zybo board}}
-We are using the new [[http://www.xilinx.com/products/design-tools/vivado/|Xilinx Vivado]] toolchain with a 25 nodes floating licence. This University System Edition license gives you access to all of the Xilinx software of this toolchain including IP exploration and high-level synthesis.\\
+We are using the [[http://www.xilinx.com/products/design-tools/vivado/|Xilinx Vivado]] toolchain with a 25 nodes floating licence. This University System Edition license gives you access to all of the Xilinx software of this toolchain including IP exploration and high-level synthesis.\\
+In a near future, we'll experiment the [[http://cdn.gowinsemi.com.cn/DS861E.pdf|GoWin GW1NSR-LV4C]] which embedds an <wrap em>ARM Cortex-M3 + FPGA</wrap> like what's done in Xilinx Zynq.\\
+Additionally, i'd like to thanks [[https://www.gowinsemi.com/|GoWin semi conductors]] //(thanks Danny)// that provided us sevreal {{ :vhdl:gowin-ministar-dev-kit.png?linkonly|Ministar development kits}} along with 30 seats floating licence :)\\
+More to come, stay tuned ;-)
-While the current Xilinx ISE toolchain gives access to all devices up to the 6<sup>th</sup> devices generation  (i.e [[http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/|Spartan6]], [[http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/|Virtex6]] ...), the Xilinx Vivado is intended to the 7<sup>th</sup> devices family (i.e [[http://www.xilinx.com/products/silicon-devices/fpga/artix-7/|Artix-7]], [[http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/|Virtex-7]] ...).
-\\
 \\
 <WRAP leftalign round info 60%>//**__Xilinx Vivado Student edition__**//
-Xilinx offers to download the Xilinx [[http://www.xilinx.com/products/design_tools/vivado/vivado-webpack.htm|Vivado Webpack]] edition. This will enable you to work on your own with the same toolchain we're using in this formation.
+Xilinx offers to download the Xilinx [[https://www.xilinx.com/support/university/students.html#software|Vivado Webpack]] edition. This will enable you to work on your own with the same toolchain we're using in this formation.
 </WRAP>
+{{ :vhdl:gowin-ministar-dev-kit.png?direct&200|GoWin Ministar dev kit}}
 <WRAP leftalign round info 60%>//**__ModelSim Student edition__**//
@@ Line 15: / Line 20: @@
 </WRAP>
-<WRAP leftalign round info 60%>//**__SDSoc toolchain__**//
+{{ :vhdl:sipeed-tang-nano-4k.png?direct&200|Sipeed Tang Nano 4k}}
-This toolchain enables you to implement as a hardware coprocessor part(s) of an application.
-</WRAP>
-{{ :vhdl:xilinx-basys3.png?direct&300|Xilinx XUP Basys3 board}}
 Below you'll find some links either related to the VHDL courses, practical exercises and some external links:
-  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_SoC_ARM_SystemC.pdf|VHDL]] main course,
+  * <wrap em>VHDL main course</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL_course.pdf|PDF]],
-  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_practical_exercises.pdf|VHDL practical exercises]],
+  * <wrap em>VHDL synthesis practical exercices</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL4synthesis_practical_exercises.pdf|PDF]],\\
-  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/R3K_Base|VHDL base files]] to download,
+  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M2|Master2 VHDL base files]] to download,
   * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]],
-  * [[http://opencores.org|Opencores]] repository,
-  * {{ :vhdl:xilinx-sdsoc-introduction.pdf | Xilinx Zynq User Guide}}.
-{{ :vhdl:xilinx-zybo.png?direct&300 |Xilinx Zynq Zybo board}}
+===== Links =====
+  * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]]
+  * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]]
+  * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 reference manual</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|PDF]]
+  * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 schematic</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7_schematic-D1.pdf|PDF]]
+  * <wrap em>[book]</wrap> The Zynq eBook [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/The_Zynq_Book_ebook_3.pdf|PDF]]
+  * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]],
+  * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]],
+  * Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform,
+  * INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]],
+  * [[http://opencores.org|Opencores]] repository.

Master SIAME | Université Toulouse 3

Master SIAME | Université Toulouse 3

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Master SIAME | Université Toulouse 3

Master SIAME | Université Toulouse 3

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