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info:vhdl [2020/10/20 11:15] francois |
info:vhdl [2021/12/23 22:37] francois |
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| ====== VHDL Xilinx/Modelsim ====== | ====== VHDL Xilinx/Modelsim ====== | ||
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| - | {{ :vhdl:parallella.png?direct&300|Parallella board}} | + | {{ :vhdl:xilinx-zybo.png?direct&300 |Xilinx Zynq Zybo board}} |
| We are using the new [[http://www.xilinx.com/products/design-tools/vivado/|Xilinx Vivado]] toolchain with a 25 nodes floating licence. This University System Edition license gives you access to all of the Xilinx software of this toolchain including IP exploration and high-level synthesis.\\ | We are using the new [[http://www.xilinx.com/products/design-tools/vivado/|Xilinx Vivado]] toolchain with a 25 nodes floating licence. This University System Edition license gives you access to all of the Xilinx software of this toolchain including IP exploration and high-level synthesis.\\ | ||
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| * {{ :vhdl:xilinx-sdsoc-introduction.pdf | Xilinx Zynq User Guide}}. | * {{ :vhdl:xilinx-sdsoc-introduction.pdf | Xilinx Zynq User Guide}}. | ||
| - | {{ :vhdl:xilinx-zybo.png?direct&300 |Xilinx Zynq Zybo board}} | + | {{ :vhdl:sipeed-tang-nano-4k.png?direct|Sipeed Tang Nano 4k}} |
info/vhdl.txt · Last modified: 2022/11/23 09:07 by francois
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