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info:vhdl [2017/11/19 12:50] francois |
info:vhdl [2017/11/20 14:03] francois |
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| ====== VHDL Xilinx/Modelsim ====== | ====== VHDL Xilinx/Modelsim ====== | ||
| + | \\ | ||
| + | <WRAP leftalign round info 60%>//**__<wrap em>[Nov.17] New M1 project available</wrap>__**// | ||
| + | We propose to experiment a [[http://m2siame.univ-tlse3.fr/teaching/francois/Projet_Hardware-Assisted-Camera_2017-2018.pdf|Hardware Assisted Camera]]. | ||
| + | This one will be based on a Zybo board (dual ARM9+FPGA) + Yocto Linux. | ||
| + | </WRAP> | ||
| \\ | \\ | ||
| {{ :vhdl:parallella.png?direct&300|Parallella board}} | {{ :vhdl:parallella.png?direct&300|Parallella board}} | ||
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| * [[http://m2siame.univ-tlse3.fr/teaching/francois/VHDL_SoC_ARM_SystemC.pdf|VHDL]] main course, | * [[http://m2siame.univ-tlse3.fr/teaching/francois/VHDL_SoC_ARM_SystemC.pdf|VHDL]] main course, | ||
| * [[http://m2siame.univ-tlse3.fr/teaching/francois/VHDL_2017.pdf|VHDL practical exercises]], | * [[http://m2siame.univ-tlse3.fr/teaching/francois/VHDL_2017.pdf|VHDL practical exercises]], | ||
| + | * [[http://m2siame.univ-tlse3.fr/teaching/francois/R3K_Base|VHDL base files]] to download, | ||
| * [[http://opencores.org|Opencores]] repository, | * [[http://opencores.org|Opencores]] repository, | ||
| * {{ :vhdl:xilinx-sdsoc-introduction.pdf | Xilinx Zynq User Guide}}. | * {{ :vhdl:xilinx-sdsoc-introduction.pdf | Xilinx Zynq User Guide}}. | ||
| {{ :vhdl:xilinx-zybo.png?direct&300 |Xilinx Zynq Zybo board}} | {{ :vhdl:xilinx-zybo.png?direct&300 |Xilinx Zynq Zybo board}} | ||
info/vhdl.txt · Last modified: 2022/11/23 09:07 by francois
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