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===== Links ===== | ===== Links ===== | ||
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+ | * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]] | ||
+ | * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]] | ||
+ | * <wrap em>board</wrap>[[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|Zybo-Z7 reference manual]] | ||
+ | * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | ||
* Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | ||
* Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform, | * Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform, | ||
- | * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | + | |
* INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]], | * INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]], | ||
* [[http://opencores.org|Opencores]] repository. | * [[http://opencores.org|Opencores]] repository. | ||