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info:vhdl [2022/01/08 19:30] francois |
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<WRAP leftalign round info 60%>//**__ModelSim Student edition__**// | <WRAP leftalign round info 60%>//**__ModelSim Student edition__**// | ||
MentorGraphics' [[http://www.modelsim.com|Modelsim]] is the simulation tool we will use. As a Master2 student, just ask them for a licence you will obtain in a few weeks. | MentorGraphics' [[http://www.modelsim.com|Modelsim]] is the simulation tool we will use. As a Master2 student, just ask them for a licence you will obtain in a few weeks. | ||
- | </WRAP> | ||
- | |||
- | <WRAP leftalign round info 60%>//**__SDSoc toolchain__**// | ||
- | This toolchain enables you to implement as a hardware coprocessor part(s) of an application. | ||
</WRAP> | </WRAP> | ||
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* <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_course.pdf|VHDL]] main course, | * <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_course.pdf|VHDL]] main course, | ||
- | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_practical_exercises.pdf|VHDL practical exercises]], | + | * <wrap em>NEW</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL4synthesis_practical_exercises.pdf|VHDL4synthesis]] practical exercises,\\ |
- | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/R3K_Base|VHDL base files]] to download, | + | |
+ | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/R3K_Base|Master2 VHDL base files]] to download, | ||
* [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]], | ||
- | * [[http://opencores.org|Opencores]] repository, | + | |
+ | ===== Links ===== | ||
+ | |||
+ | * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]] | ||
+ | * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]] | ||
+ | * <wrap em>board</wrap>[[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|Zybo-Z7 reference manual]] | ||
+ | * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]], | ||
+ | |||
+ | * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]], | ||
+ | * Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform, | ||
+ | |||
+ | * INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]], | ||
+ | * [[http://opencores.org|Opencores]] repository. | ||