====== VHDL Xilinx/Modelsim ======
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{{ :vhdl:xilinx-zybo.png?direct&250|Xilinx Zynq Zybo board}}

We are using the [[http://www.xilinx.com/products/design-tools/vivado/|Xilinx Vivado]] toolchain with a 25 nodes floating licence. This University System Edition license gives you access to all of the Xilinx software of this toolchain including IP exploration and high-level synthesis.\\

In a near future, we'll experiment the [[http://cdn.gowinsemi.com.cn/DS861E.pdf|GoWin GW1NSR-LV4C]] which embedds an <wrap em>ARM Cortex-M3 + FPGA</wrap> like what's done in Xilinx Zynq.\\
Additionally, i'd like to thanks [[https://www.gowinsemi.com/|GoWin semi conductors]] //(thanks Danny)// that provided us sevreal {{ :vhdl:gowin-ministar-dev-kit.png?linkonly|Ministar development kits}} along with 30 seats floating licence :)\\
More to come, stay tuned ;-)

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<WRAP leftalign round info 60%>//**__Xilinx Vivado Student edition__**//
Xilinx offers to download the Xilinx [[https://www.xilinx.com/support/university/students.html#software|Vivado Webpack]] edition. This will enable you to work on your own with the same toolchain we're using in this formation.
</WRAP>

{{ :vhdl:gowin-ministar-dev-kit.png?direct&200|GoWin Ministar dev kit}}

<WRAP leftalign round info 60%>//**__ModelSim Student edition__**//
MentorGraphics' [[http://www.modelsim.com|Modelsim]] is the simulation tool we will use. As a Master2 student, just ask them for a licence you will obtain in a few weeks.
</WRAP>

{{ :vhdl:sipeed-tang-nano-4k.png?direct&200|Sipeed Tang Nano 4k}}

Below you'll find some links either related to the VHDL courses, practical exercises and some external links:

  * <wrap em>VHDL main course</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL_course.pdf|PDF]],
  * <wrap em>VHDL synthesis practical exercices</wrap> [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/VHDL4synthesis_practical_exercises.pdf|PDF]],\\

  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M1|Master1 VHDL base files]] and [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-VHDL/M2|Master2 VHDL base files]] to download,
  * [[http://m2siame.univ-tlse3.fr/teaching/francois/UE-M1-VHDL/VHDL_exam.pdf|VHDL exam]],

===== Links =====

  * Cristian Sisterna's Zynq Architecture [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Sisternal_Zynq-architecture_C7T.pdf|PDF]]
  * Xilinx Zynq Architecture slides [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/Xilinx_Zynq-architecture-v14.2_2012.pdf|PDF]]
  * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 reference manual</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7-reference-manual-B.pdf|PDF]]
  * <wrap em>[board]</wrap> Digilent <wrap em>Zybo-Z7 schematic</wrap> [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/ZYBO-Z7_schematic-D1.pdf|PDF]]

  * <wrap em>[book]</wrap> The Zynq eBook [[https://m2siame.univ-tlse3.fr/teaching/francois/UE-M2-VHDL/The_Zynq_Book_ebook_3.pdf|PDF]]
  * Atlassian [[https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview|Xilinx wiki]],
  * Eric Peronnin's introduction to [[https://www.youtube.com/watch?v=vK9yKtEK-R4|Zynq platform]],
  * Eric Peronnin's [[https://www.youtube.com/watch?v=djMAXkvw7UI|VHDL project creation]] on a Zynq platform,

  * INRIA Olivier Sentieys [[http://people.rennes.inria.fr/Olivier.Sentieys/teach/VHDL_Logic_Synthesis_2019.pdf|FIR filter synthesis]],
  * [[http://opencores.org|Opencores]] repository.